(a) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same. In particular, the present invention relates to a nonvolatile semiconductor memory, such as a virtual ground split gate EPROM, in which insulating films and erasing gates are alternately formed in spaces between each adjacent two of control gates, and a method for manufacturing such a nonvolatile semiconductor memory device.
(b) Description of the Related Art
A virtual ground split gate EPROM (referred to as simply EPROM hereinafter) has been proposed for increasing the scale in integration and the yield of EPROMs. A conventional EPROM will be described with reference to drawings. FIG. 1 shows a schematic plan view of the conventional EPROM while FIG. 2 is a cross-sectional view of the same along line B--B in FIG. 1.
Referring to FIGS. 1 and 2, n.sup.+ -type buried diffusion (diffused) layers 14 constituting source/drain regions are formed within a surface region of a p-type silicon substrate 1 such that the buried diffusion layers 14 extend parallel to one anther in a column direction (vertical direction as viewed in FIG. 1). The n.sup.+ -type buried diffusion layers 14 are covered by a relatively thick silicon oxide film 15. Element separation films or field oxide film 2 are formed such that they extend parallel to one another on the substrate in a row direction. Floating gates 4 overlying the substrate 1 are formed in a matrix such that each of the floating gates 4 partially overlaps a corresponding one of the buried diffusion layers 14. Further, control gates 6 overly the respective rows of floating gates 4 to extend in the row direction, the control gates 6 constituting laminate gate structures together with the respective floating gates 4. The surfaces of the control gates 6 are covered by a silicon oxide film 7. One of each adjacent two of spaces formed between two adjacent gate structures is filled with erasing gates 12. The entire surface of the substrate is further covered by a silicon oxide film 16.
Referring to FIG. 3 which shows an equivalent circuit of the memory cell array shown in FIG. 1, the n.sup.+ -type buried diffusion layers 14 form bit lines B1, B2, etc., while the control gates 6 form word lines W1, W2, etc. The channel portion of each memory cell includes two split regions as shown in FIG. 3. In the first region, the control gate 6 opposes the channel region with the intervention of the floating gate 4 disposed therebetween. In the second region, the control gate 6 directly opposes the channel portion. This structure is called a "split gate" type.
To read out data from a memory cell (2, 1) in FIG. 3, for example, i.e., a memory cell disposed at a second row and a first column, voltage of 5 V is applied to a word line W2, a bit line B1 is grounded, and a voltage of 1.5 V is applied to a bit line B2. Other non-selected word lines W1, W3, W4 etc. are grounded while other non-selected bit lines B3, B4 etc. are left in a floating state.
To write data into the memory cell (2, 1), a voltage of 12 V is applied to the word line W2, the bit line B1 is grounded, and a voltage of 7 V is applied to the bit line B2. Other non-selected word lines W1, W3, W4 etc. are grounded. With this state, hot electrons are generated in the channel of the memory cell (2, 1) and injected into the floating gate 4 thereof.
To erase data in the memory cells, the word lines W1, W2 etc. are grounded and a voltage of 20 V, for example, is applied to erasing gates 12 so as to withdraw carriers from the floating gates 4 to the erasing gates 12.
As described above, the conventional virtual ground split gate EPROM has two important structural features, i.e., having the n.sup.+ -type buried diffusion layers as bit lines, and having serially connected section transistors, so called of split gate type, in each memory cell having a floating gate. The use of n.sup.+ -type buried bit lines greatly reduces the number of contacts required in the memory cell array, thereby increasing the scale in integration and the yield of the device.
By the serial selection transistors provided for each memory cell, it is possible to avoid the problem that ON current erroneously flows through non-selected memory cells connected to a selected bit line even when a voltage is applied to the floating gates of these non-selected memory cells due to the voltage on the bit line to thereby turn-on the non-selected memory cells. This greatly reduces the restriction on the drain voltage for programming. An EPROM of this type is described in Patent Publication No. JP-A-1990-292870, for example.
Next, a conventional method for manufacturing an EPROM of the type as described above will be described with reference to FIGS. 4A and 4B showing consecutive steps of the process in memory cell array section 20 and peripheral circuit section 30.
An unillustrated photoresist film is selectively formed on a p-type silicon substrate 1, then n.sup.+ -type buried diffusion layers not shown in FIGS. 4A and 4B and constituting bit lines are formed by ion implantation using the photoresist film as a mask.
After removal of the photoresist film, a silicon oxide film is deposited over the entire surface of the substrate 1 by using a CVD technology. The silicon oxide film is then subjected to patterning so as to form field oxide films 2 within both the cell array section 20 and the peripheral circuit section 30. Thereafter, a gate oxide films 3 is formed, and a 2000 angstrom thick polycrystalline silicon (polysilicon) film for floating gates is deposited thereon. The polysilicon film is subjected to dry etching using a photoresist mask to be formed in a plurality of parallel strips.
After forming consecutively an inter-gate insulating film 5 and a 3500 angstrom thick polysilicon film for control gates, both the polysilicon film for control gates and the polysilicon film for floating gates are subjected to patterning, thereby forming laminate gates structures each including a part of the strip control gate 6 and the separate floating gate 4. At this time, the polysilicon films are removed from the peripheral circuit section 30.
By subsequent thermal oxidization, a 100 angstrom thick silicon oxide film 7 is formed on the control gates, on the floating gates 6, and on the exposed portions of the substrate surface. The silicon oxide film 7 serves as a gate oxide film within the peripheral circuit section 30. Subsequently, a polysilicon film 12a for use in forming erasing gates is deposited to a thickness of about 2500 angstroms such that the spaces between two adjacent gate structures are filled with the polysilicon film 12a. Thereafter, a photoresist film 17 is formed using photolithography, thus obtaining the structure of FIG. 4A.
Subsequently, the polysilicon film 12a is patterned by a dry etching technology using the photoresist film 17 as a mask so as to form erasing gates 12 which bury one of each two of spaces formed between two adjacent gate structures and so as to form gate electrodes 13 within the peripheral circuit section 30. Thereafter, a silicon oxide film 16 is deposited on the entire surface including the vacant spaces between the gate structures as well as the surfaces of the erasing gates by using a CVD technology, thereby obtaining the structure of FIG. 4B. Finally, remaining processes such as formation of interconnets are carried out to complete a nonvolatile semiconductor memory device.
The conventional EPROM as described above has the following drawbacks. That is, in the conventional EPROM, the erasing gates 12 in the cell array section 20 and the gate electrodes 13 in the peripheral circuit are made from the same polysilicon film and are patterned using a photolithographic dry etching technology during the same patterning step. At this time, it is necessary within the cell array section to remove the polysilicon film 12a for the erasing gates buried in the other of each two of the spaces formed between the gate structures. The thickness of the polysilicon film 12a is as high as about 8000 angstroms (2000+3500+2500). In contrast, the thickness of the polysilicon film within the peripheral circuit section is about 2500 angstroms. Therefore, the latter area is subjected to excessive etching during the time period required to remove the polysilicon film having a thickness of 5500 angstroms.
Although the 100 angstrom thick gate oxide film 7 formed by thermal oxidization may be desired to stop excessive etching, the thickness of the silicon oxide film 7 is insufficient to stop the excessive etching. Therefore, the surface of the silicon substrate 1 is subjected to etching, so that the silicon surface includes an etched portion 18 shown in FIG. 4B. The etched portion 18 causes variations in the device sizes (channel length, for example) of transistors of the peripheral circuit, resulting in increased variations in the characteristics of the transistors. Further, the yield of the device decreases accordingly.
The conventional EPROM has another drawback in that a difference in level is produced at the boundary between the cell array section and the peripheral circuit section before the step for forming interconnects. That is, since a plurality of thin films are laminated within the cell array section 20, the total thickness of the layers within the cell array section 20 is much greater than that within the peripheral circuit section 30 to produce the difference in level. This may cause a defects or breakage in the overlying interconnects, resulting in a decreased manufacturing yield of the memory device.